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Typical Applications:
-Set Top Boxes -Stereo Amplifiers -DVD Players -Portable Audio Products
New Feature Zero Amplitude Wiper Switching
Low Noise, Low Cost, High End Features, Dual Audio Log Potentiometer
X9460
Dual Audio Control Digitally Controlled Potentiometer (XDCPTM)
FEATURES * Dual audio control - Two 32 taps Log pots * Zero Amplitude Wiper Switching * 2-wire serial interface 4 cascadable slave byte addresses [A1,A0] * Total resistance: 33K each XDCP (Typical) * Dual Voltage Operation V+/V- = 2.7 to 5.5V * Temp Range = -40oC to +85 oC * Package Options 14-Lead TSSOP AUDIO PERFORMANCE * 0 to - 62dB volume control * -92dB Mute --Power up to mute position * SNR -96dB * THD+N: -95dB @1k HZ * Crosstalk rejection: -102dB @ 1k HZ * Channel-to-channel variation: 0.1dB * 3dB-cutoff: 100kHz DESCRIPTION The X9460 integrates two digitally controlled potentiometer (XDCP) on a monolithic CMOS integrated circuit. The two XDCPs can be used as stereo gain controls in audio applications. Read/Write operations can directly access each channel independently or both channels simultaneously. Increment/ Decrement can adjust each channel independently or both channels simultaneously. The X9460 contains a zero amplitude wiper switching circuit that delays wiper changes until the next zero crossing of the audio signal. The digitally controlled potentiometer is implemented using 31 polysilicon resistors in a log array. Between each of the resistors are tap points connected to the wiper terminal through switches. The XDCPs are designed to minimize wiper noise to avoid pops and clicks during audio volume transitions. The position of the wiper on the array is controlled by the user through the 2-wire serial bus interface. Power up reset the wiper to the mute position.
SIMPLIFIED FUNCTIONAL DIAGRAM
VCC Power On Recall mute data address IC bus
2
RH-Left
RH-Right
V+
62dB total Step Size -1dB -2dB # of Steps 11 10 5 4 1
BUS INTERFACE CONTROL & REGISTER
select inc / dec
POT Left
POT Right
-3dB -4dB Mute
VSS
RW-Left RL-Left
RW-Right
RL-Right
V-
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X9460
DETAILED FUNCTIONAL DIAGRAM
VCC
V+
Power On Recall mute SCL SDA A0 A1 INTERFACE AND CONTROL CIRCUITRY
WIPER COUNTER REGISTER (WCR) POT Left
RH-Left
RL-Left RW-Left RW-Right
8 DATA WIPER COUNTER REGISTER (WCR) POT Right RH-Right
RL-Right
VSS
V-
TYPICAL APPLICATION X9460
Gain / Volume Control Left Channel Control Right Channel Control Simultaneous Left and Right Channel Control Power up in Mute.
Audio => RHL, RHR RWL, RWR => Amplifier Audio DAC
2 XDCP
Audio Amplifier Left
Audio Amplifier Right
Controller
Serial Bus
EEPROM
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X9460
PIN CONFIGURATION
TSSOP SDA SCL VCC V+ VSS A1 A0 14 1 13 2 3 12 4 X9460 11 5 10 6 9 8 7 VRH-right RL-right RW-right RH-left RL-left RW-left
PIN ASSIGNMENTS Pin (TSSOP)
1 2 3 4 5 6 7 8 9 10 11 12 13 14
Symbol
SDA SCL VCC V+ VSS A1 A0 RW-left RL-left RH-left RW-right RL-right RH-right VSerial Data Serial Clock System Supply Voltage Positive Analog Supply System Ground Device Address Device Address
Function
Wiper terminal of the Left Potentiometer Negative terminal of the Left Potentiometer Positive terminal of the Left Potentiometer Wiper terminal of the Right Potentiometer Negative terminal of the Right Potentiometer Positive terminal of the Right Potentiometer Negative Analog Supply
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X9460
DETAILED PIN DESCRIPTION: Host Interface Pins SERIAL CLOCK (SCL) The SCL input clocks data into and out of the X9460. SERIAL DATA (SDA) SDA is a bidirectional pin used to transfer data into and out of the device. It is an open drain output and may be wire-ORed with any number of open drain or open collector outputs. An open drain output requires the use of a pull-up resistor. For selecting typical values, refer to the guidelines for calculating typical values on the bus pull-up resistors graph. DEVICE ADDRESS (A1- A0) The Address inputs are used to set the least significant 2 bits of the 8-bit Slave Byte Address. A match in the slave address serial data stream must be made with the Address input in order to initiate communication with the X9460. Up to 4 X9460s may be directly connected to a single I2C serial bus. If left floating, these pins are internally pulled to ground. Slave Byte (bits, MSB-LSB) = 0101 0 A1 A0 R/W Potentiometer Pins RH-LEFT, RL-LEFT, RH-RIGHT, RL-RIGHT The RH and RL inputs are equivalent to the terminal connections on either end of a mechanical potentiometer. RW-LEFT, RW-RIGHT The wiper outputs are equivalent to the wiper output of a mechanical potentiometer. Supply Pins ANALOG SUPPLY V- AND V+ The positive power supply for the DCP analog control section is connected to V+. The negative power supply for the DCP analog control section is connected to V-. Digital Supplies VCC, VSS The power supplies for the digital control sections. Power Up and Down Recommendations There are no restrictions on the power-up condition of VCC, V+ and V- and the voltages applied to the potentiometer pins provided that the Vcc and V+ are more positive or equal to the voltage at RH, RL , and Rw, ie. Vcc, V+ > RH, RL, Rw. At all times, the voltages on the potentiometer pins must be less than V+ and more than V-. The following VCC ramp rate spec is always in effect. 0.2 V/ms < VCC ramp < 50 V/ms The VSS pin is always connected to the system common or ground. VH, VL, VW are the voltages on the RH, RL, and RW potentiometer pins. X9460 PRINCIPLES OF OPERATION The X9460 is a highly integrated microcircuit incorporating two resistor arrays with their associated registers, counters and the serial interface logic providing direct communication between the host and the DCP potentiometers. This section provides detailed description as following: - Resistor Array Description - Serial Interface Description - Command Set and Register Information Description RESISTOR ARRAY DESCRIPTION The X9460 is comprised of two resistor arrays. Each array contains 31 discrete resistive segments that are connected in series. The physical ends of each array are equivalent to the fixed terminals of a mechanical potentiometer (RH and RL inputs). Tables 1 and 2 provide a description of the step size and tap positions. At both ends of each array and between each resistor segment is a CMOS switch connected to the wiper (RW) output. Within each individual array only one switch may be turned on at a time. These switches are controlled by the Wiper Counter Register (WCR). The five bits of the WCR are decoded to select, and enable, one of thirty-two switches. Table 1. Total -62dB range Plus Mute Position Step Size
-1 dB - 2 dB - 3 dB - 4 dB Mute
# of Steps
11 steps 10 steps 5 steps 4 steps 1 step
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X9460
Table 2. Wiper Tap Position vs dB. Tap Position, n
for n = 20 to 31 for n = 10 to 19 for n = 5 to 9 for n = 1 to 4 n=0
dB
n - 31 2n-51 3n-61 4n-66 -92
Min/Max dB
-11 / 0 -31 / -13 -46 / -34 -62 / -50 -92
Start Condition All commands to the X9460 are preceded by the start condition, which is a HIGH to LOW transition of SDA while SCL is HIGH. The X9460 continuously monitors the SDA and SCL lines for the start condition and will not respond to any command until this condition is met. Stop Condition All communications must be terminated by a stop condition, which is a LOW to HIGH transition of SDA while SCL is HIGH. Acknowledge Acknowledge is a software convention used to provide a positive handshake between the master and slave devices on the bus to indicate the successful receipt of data. The transmitting device, either the master or the slave, will release the SDA bus after transmitting eight bits. The master generates a ninth clock cycle and during this period the receiver pulls the SDA line LOW to acknowledge that it successfully received the eight bits of data. The X9460 will respond with an acknowledge: 1) after recognition of a start condition and after an identification and slave address byte, and 2) again after each successful receipt of the instruction or databyte. See Figure 1. Invalid Commands For any invalid commands or unrecognizable addresses, the X9460 will NOT acknowledge and return the X9460 to the idle state.
SERIAL INTERFACE DESCRIPTION Serial Interface The X9460 supports a bidirectional bus oriented protocol. The protocol defines any device that sends data onto the bus as a transmitter and the receiving device as the receiver. The device controlling the transfer is a master and the device being controlled is the slave. The master will always initiate data transfers and provide the clock for both transmit and receive operations. The X9460 is a slave device in all applications. Clock and Data Conventions Data states on the SDA line can change only during SCL LOW periods. SDA state changes during SCL HIGH are reserved for indicating start and stop conditions.
Figure 1. Acknowledge Response from Receiver
SCL FROM MASTER
1
8
9
DATA OUTPUT FROM TRANSMITTER DATA OUTPUT FROM RECEIVER START ACKNOWLEDGE
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X9460
COMMAND SET AND REGISTER DESCRIPTION DEVICE ADDRESSING Following a start condition the master must output the Slave Byte Address of the slave it is accessing. The most significant four bits of the slave address are the device type identifier (refer to Figure 2 below). For the X9460 this is fixed as 0101. Figure 2. Slave Byte Address
DEVICE TYPE IDENTIFIER
this circuit is disabled. The last two bits, LT (left POT enable) and RT (right POT enable), select which of the two potentiometers is affected by the instruction. Several instructions require a three-byte sequence to complete. These instructions transfer data between the host and the X9460. These instructions are: Read Wiper Counter Register, Write Wiper Counter Register. The sequence of operations is shown in Figure 4 and 5. The four-byte command is used for write command for both right and left pots (Figure 6). Special Commands Increment / Decrement Instruction. The Increment/ Decrement command is different from the other commands. Once the command is issued and the X9460 has responded with an acknowledge, the master can clock the selected wiper up and/or down. For each SCL clock pulse (tHIGH) while SDA is HIGH, the selected wiper will move one resistor segment towards the RH terminal. Similarly, for each SCL clock pulse while SDA is LOW, the selected wiper will move one resistor segment towards the RL terminal. A detailed illustration of the sequence and timing for this operation are shown in Figures 7 and 8 respectively. Wiper Counter Register The X9460 contains two Wiper Counter Registers. The Wiper Counter Register output is decoded to select one of thirty-two switches along its resistor array. The Write Wiper Counter Register command directly sets the WCR to a value. The Increment/Decrement instruction steps the register value up or down one to multiple times. The WCR is a volatile register (Table 3) and is reset to the mute position (tap 0, "zero") at power-up. Table 3. Wiper Counter Registers, 5-bit - volatile:
WCR4 WCR3 WCR2 WCR1 WCR0 (LSB) (MSB)
0
1
0
1
0
A1
A0
R/W
DEVICE ADDRESS
The next three bits of the Slave Byte Address are the device address. The device address is defined by the A1-A0 inputs. The X9460 compares the serial data stream with the Slave Byte Address; a successful compare is required for the X9460 to respond with an acknowledge. The A1-A0 inputs can be actively driven by CMOS input signals or tied to VCC or VSS. The R/W bit sets the device for read or write operations. Command Set After a Slave Byte Address match, the next byte sent contains the Command and register pointer information. The four most significant bits are the Command. The next bit is a "X" (don't care) set to zero. Figure 3. Command Byte Format
this bit not used, set to 0
I3
I2
I1
I0
0
ZD
RT
LT
INSTRUCTIONS
WIPER COUNTER SELECT
The X9460 contains one 5-bit Wiper Counter Register for each DCP. (Two 5-bit registers in total.)
The ZD bit enables and disables the Zero Amplitude Wiper Switching circuit. When ZD=1, the wiper switches will turn on when close-to-zero amplitude is detected across the potentiometer pins. When ZD=0,
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X9460
Table 2a. Command Set Instruction
Read Wiper Write Left Wiper Counter Write Right Wiper Counter Write Both Wiper Counters Inc/Dec Left Wiper Counter Inc/Dec Right Wiper Counter Inc/Dec Both Wiper Counters
Notes: "1/0" = data is one or zero
I3
I2
Instruction Set I1 I0 X ZD RT LT
Operation
LSB of Slave Byte=1, no command required Slave will return Left then Right Data Write new value to the Wiper Counter Register Write new value to the Wiper Counter Register Write new value to the Wiper Counter Register
1 1 1
0 0 0
1 1 1
0 0 0
0 0 0
1/0 1/0 1/0
0 1 1
1 0 1
0 0 0
0 0 0
1 1 1
0 0 0
0 0 0
1/0 1/0 1/0
0 1 1
1 0 1
Enable Increment/decrement of the Control Latch Enable Increment/decrement of the Control Latch Enable Increment/decrement of the Control Latch
Figure 4. Three-Byte Command Sequence (Read)
SCL SDA S T A R T 0 1 0 1 0 1 A1 A0 R/W A C K 0 0 0 0 0 0 W C R 4 W C R 3 W C R 2 W C R 1 W C R 0 A C K
0 0
0 0
0 0 W C R 4 W C R 3 W C R 2 W C R 1 W C R 0 A C K S T O P
DEVICE TYPE IDENTIFIER
LEFT POT DATA BYTE
RIGHT POT DATA BYTE
Figure 5. Three-Byte Command Sequence (Write)
SCL SDA S T A R T 0 1 0 1 0 0 A1 A0 R/W A C K
1 I3
0 I2
1
0
0 0 ZD RT LT A C K
0 0
0 0
0 0 W C R 4 W C R 3 W C R 2 W C R 1 W C R 0 A C K S T O P
I1 I0
DEVICE TYPE IDENTIFIER INSTRUCTION BYTE
RIGHT or LEFT POT DATA BYTE
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X9460
Figure 6. Four-Byte Command Sequence (Write)
SCL
SDA
0
1
0
1
00
1
1
00
0 W C R 1
000 WW W W CA 0 00CC C RR R RC 432 0K RIGHT POT DATA BYTE W C R 1 W C AS R CT 0 KO P
S 0 1 0 1 0 A1 A0 R/W A I3 I2 T C A K R DEVICE TYPE T IDENTIFIER INSTRUCTION BYTE
WW W I1 I0 0 ZD RT LT A 0 0 0 C C C C RR R K 432 LEFT POT DATA BYTE
Figure 7. Increment/Decrement Command Sequence (Write)
SCL
SDA S T A R T 0 1 0 1 0
0 A1 A0 R/W A C K
0 I3
0 I2
1 I1
0 I0
0 0 ZD RT LT A C K I N C 1 I N C 2 I N C n D E C 1 D E C n S T O P
DEVICE TYPE IDENTIFIER
INSTRUCTION BYTE
INC and DEC active
Figure 8. Increment/Decrement Timing Limits
INC/DEC CMD ISSUED SCL
t WRID
SDA
RW
VOLTAGE OUT
Wiper can move within 10secs after the falling edge of SCL
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X9460
INSTRUCTION FORMATS Read Wiper Counter Register
device S device type identifier addresses T A R01010AA 10 T Right wiper position M (sent by slave on SDA) A LLLLLC RRRRR 000DDDDD K000DDDDD 43210 43210 Left wiper position (sent by slave on SDA)
Write Wiper Counter Register
device S device type identifier addresses T A R AA T0101010 Left or Right wiper position S SS (sent by master on SDA) A T A C CO ZRLK DDDDDKP 10100 000 DTT 43210 instruction opcode wiper addresses
R/W=1
S A C K
M A C K
S T O P
Write Both Wiper Counter Registers
device S device type identifier addresses T A R AA 01010 10 T instruction wiper S opcode addresses A C Z K10100 11 D Left wiper position (sent by master on SDA) Right wiper position (sent by master on SDA)
R/W=0
S A C K
Increment/Decrement Wiper Counter Register
S device type identifier T A R0101 T device addresses 0 A1 A0
R/W=0
R/W=0
S A C LLLLL K000DDDDD 43210
S A C RRRRR K 000DDDDD 43210
S A C K
S T O P
instruction wiper S opcode addresses A C 0 0 1 0 0 ZD RT LT K
increment/decrement S (sent by master on SDA) A C I/D I/D . . . . I/D I/D K
S T O P
Definitions: (1) "MACK"/"SACK": stands for the acknowledge sent by the master/slave. (2) "A1 ~ A0": stands for the device addresses sent by the master. (3) "I": stands for the increment operation, SDA held high during active SCL phase (high). (4) "D": stands for the decrement operation, SDA held low during active SCL phase (high).
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X9460
ABSOLUTE MAXIMUM RATINGS* Temperature under Bias .................... -65C to +135C Storage Temperature.........................-65C to +150C Voltage on SDA, SCL or any Address Input with Respect to VSS ................................-1V to +6V Voltage on V+ (referenced to VSS)......................... +6V Voltage on V- (referenced to VSS)........................... -6V (V+) - (V-).............................................................. 12V Any RH .................................................................... V+ Any RL ...................................................................... VLead Temperature (Soldering, 10 seconds) ...... 300C IW max (10 secs) ............................................... 3mA RECOMMENDED OPERATING CONDITIONS Temp
Industrial
*Stresses above those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress rating only and the functional operation of the device at these or any other conditions above those listed in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.
Min.
-40C
Max.
+85C
Device
X9460V14-2.7
Supply Voltage (VCC)
2.7V to 5.5V
V- Limits
-5.5V to -2.7V
V+ Limits
+2.7V to +5.5V
ANALOG CHARACTERISTICS (Over the recommended operating conditions unless otherwise specified)(1) Symbol
Dynamic
Parameter
Performance(2)(3) Control Range Mute Mode
Min. Typ.
-62 -92 -96 -95 -102 -105 100 -1 -0.2 -0.4 -0.6 -0.8 -0.1
Max.
0
Unit
dB dB dB dB dB dB kHz @1V rms
Test Conditions
SNR THD + N XTalk
Signal Noise Ratios (Unweighted) Total Harmonic Distortion + Noise DCP Isolation Digital Feedthrough (Peak Component) -3db Cutoff Frequency
@1V rms @ 1kHz, Tap = -6dB @1V rms @ 1kHz, Tap = -6dB @1kHz, tap = -6dB tap = -6dB
DC Accuracy Step Size Step Size Error Step Size Error Step Size Error Step Size Error DCP to DCP Matching -4 +0.2 +0.4 +0.6 +0.8 0.1 dB dB dB dB dB dB Steps of -1, -2, -3, -4 dB For -1dB steps For -2dB steps For -3dB steps For -4dB steps
Notes: (1) VCC = | V- | VCC Ramp up timing 0.2 V/ms < Vcc Ramp Rate < 50 V/ms (2) This parameter is guaranteed by design and characterization (3) TA = 25oC, VCC = 5.0V; 20 Hz to 20kHz Measurement Bandwidth with 80kHZ filter, input signal 1Vrms, 1kHz Sine Wave.
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X9460
ANALOG CHARACTERISTICS (Over the recommended operating conditions unless otherwise specified)(1) ANALOG INPUTS Symbol
VTERM RTOTAL Cin
(4)
Parameter
Voltage on RL, RW, and RH pins End to End Resistance Input Capacitance RL, RH, RW Wiper Current Wiper Resistance Voltage on V- pin Voltage on V+ pin Noise
Min.
V-20
Typ.
Max.
V+ +20
Unit
V % pF mA V V Vrms PPM/C
Test Conditions
Typical 33K TA = 25oC Wiper Current = 3mA
25 -3 100 -5.5 +2.7 2 -300 +3 200 -2.7 +5.5
IW(2) RW VV+
20 HZ to 20KHZ, Grounded Input @ -6dB tap
TCR(2)
Temperature Coefficient of resistance
D.C. OPERATING CHARACTERISTICS (Over the recommended operating conditions unless otherwise specified.)(1) Limits Symbol
ICC1 ISB ILI Iai ILO VIH VIL VOL
Parameter
VCC Supply Current (Move Wiper, Write, Read) VCC Current (Standby) Input Leakage Current Analog Input Leakage Output Leakage Current Input HIGH Voltage Input LOW Voltage Output LOW Voltage
Min.
Typ.
200 3 1 0.1
Max.
300
Units
A A
Test Conditions
fSCL = 400kHz, SDA = Open, Other Inputs = VSS SCL = SDA = VCC, Addr. = VSS VIN = VSS to VCC VIN = V- to V+ with all other analog inputs floating VOUT = VSS to VCC
10
A A
10 VCC x 0.7 -0.5 VCC + 0.5 VCC x 0.1 0.4
A V V V
IOL = 3mA
CAPACITANCE Symbol
CI/O
(4)
Test
Input/Output Capacitance (SDA) Input Capacitance (A0, A1, A2 and SCL)
Max.
8 6
Units
pF pF
Test Conditions
VI/O = 0V VIN = 0V
CIN(4)
Notes: (4) This parameter is not 100% tested.
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X9460
A.C. TEST CONDITIONS Input Pulse Levels
Input Rise and Fall Times Input and Output Timing Level VCC x 0.1 to VCC x 0.9 10ns VCC x 0.5
EQUIVALENT A.C. LOAD CIRCUIT
5V 1533 SDA OUTPUT 100pF
AC TIMING (Over recommended operating conditions) Symbol
fSCL tCYC tHIGH tLOW tSU:STA tHD:STA tSU:STO tSU:DAT tHD:DAT tR tF
(2) (2) (2)
Parameter
Clock Frequency Clock Cycle Time Clock High Time Clock Low Time Start Setup Time Start Hold Time Stop Setup Time SDA Data Input Setup Time SDA Data Input Hold Time SCL and SDA Rise Time SCL and SDA Fall Time SCL Low to SDA Data Output Valid Time SDA Data Output Hold Time Noise Suppression Time Constant at SCL and SDA inputs Bus Free Time (Prior to Any Transmission) A0, A0, A1(2) A1(2)
Min.
2500 600 1300 600 600 600 500 50
Max.
400
Units
kHz ns ns ns ns ns ns ns ns
300 300 900 50 50 1300 0 0
ns ns ns ns ns ns ns ns
tAA
tDH(2) TI(2) tBUF
(2)
tSU:WPA tHD:WPA
DCP TIMING(2) Symbol
tWRPO tWRL tWRID
Parameter
Wiper Response Time After The Third (Last) Power Supply Is Stable Wiper Response Time After Instruction Issued (All Load Instructions) Wiper Response Time From An Active SCL Edge (Increment/Decrement Instruction)
Min.
Max.
10 10 10
Units
s s s
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X9460
TIMING DIAGRAMS Figure 9. START and STOP Timing (START) tR SCL tSU:STA SDA tHD:STA tR tF tSU:STO tF (STOP)
Figure 10. Input Timing tCYC SCL tLOW SDA tSU:DAT Figure 11. Output Timing tHD:DAT tBUF tHIGH
SCL
SDA tAA Figure 12. DCP Timing (for All Load Instructions) (STOP) SCL tDH
SDA
LSB tWRL
VWx
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X9460
TYPICAL PERFORMANCE CHARACTERISTICS (VCC,V+ = 5.0V,V- = -5.0V, TA = + 25 C, unless otherwise noted)
FFT Spectrum
(with 1kHz 1Vrms input, tap = -6dB)
+0 -1 0 -2 0 -3 0 -4 0 -5 0 -6 0 -7 0 d B V -8 0 -9 0 -1 0 0 -1 1 0 -1 2 0 -1 3 0 -1 4 0 -1 5 0 -1 6 0 -1 7 0 -1 8 0
20 50 100 200 500 1k 2k 5k 10k 20k
Hz
Figure 13. Single Tone Frequency Response
THD+N vs Frequency
(with 80kHz low-pass filter, tap = -6dB)
-6 0 -6 5 -7 0 -7 5 -8 0 -8 5 d B -9 0 -9 5 -1 00 -1 05 -1 10 -1 15 -1 20 20
50
100
200
500 Hz
1k
2k
5k
10k
20k
Figure 14. THD + N
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X9460
TYPICAL PERFORMANCE CHARACTERISTICS (VCC,V+ = 5.0V,V- = -5.0V, TA = + 25 C, unless otherwise noted)
Mut e Mod e
+0 -10 -20 -30 -40 -50 -60 d B V -70 -80 -90 -100 -110 -120 -130 -140 20 50 100 200 500 Hz 1k 2k 5k 10k 20k
Figure 15. Mute
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X9460
PACKAGING INFORMATION 14-Lead Plastic, TSSOP, Package Type V
.025 (.65) BSC
.169 (4.3) .252 (6.4) BSC .177 (4.5)
.193 (4.9) .200 (5.1)
.047 (1.20) .0075 (.19) .0118 (.30) .002 (.05) .006 (.15)
.010 (.25) Gage Plane 0 - 8 .019 (.50) .029 (.75) Detail A (20X) Seating Plane
.031 (.80) .041 (1.05) See Detail "A"
NOTE: ALL DIMENSIONS IN INCHES (IN PARENTHESES IN MILLIMETERS)
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X9460
ORDERING INFORMATION X9460 Device K P T V VCC Limits
Blank = 5V 10% -2.7 = 2.7 to 5.5V Temperature Range Blank = Commercial = 0C to +70C I= Industrial = -40C to +85C Package V14 = 14-Lead TSSOP
Potentiometer Organization
K= Left Pot 33K 20% Right Pot 33K 20%
X9460 TSSOP 14L Top Mark Instructions
Commercial Industrial X9460KV EYWW I X9460KV EYWW G
5.0 volt 2.7 volt
X9460KV EYWW X9460KV EYWW F
LIMITED WARRANTY
(c)Xicor, Inc. 2000 Patents Pending
Devices sold by Xicor, Inc. are covered by the warranty and patent indemnification provisions appearing in its Terms of Sale only. Xicor, Inc. makes no warranty, express, statutory, implied, or by description regarding the information set forth herein or regarding the freedom of the described devices from patent infringement. Xicor, Inc. makes no warranty of merchantability or fitness for any purpose. Xicor, Inc. reserves the right to discontinue production and change specifications and prices at any time and without notice. Xicor, Inc. assumes no responsibility for the use of any circuitry other than circuitry embodied in a Xicor, Inc. product. No other circuits, patents, or licenses are implied. TRADEMARK DISCLAIMER: Xicor and the Xicor logo are registered trademarks of Xicor, Inc. AutoStore, Direct Write, Block Lock, SerialFlash, MPS, and XDCP are also trademarks of Xicor, Inc. All others belong to their respective owners. U.S. PATENTS Xicor products are covered by one or more of the following U.S. Patents: 4,326,134; 4,393,481; 4,404,475; 4,450,402; 4,486,769; 4,488,060; 4,520,461; 4,533,846; 4,599,706; 4,617,652; 4,668,932; 4,752,912; 4,829,482; 4,874,967; 4,883,976; 4,980,859; 5,012,132; 5,003,197; 5,023,694; 5,084,667; 5,153,880; 5,153,691; 5,161,137; 5,219,774; 5,270,927; 5,324,676; 5,434,396; 5,544,103; 5,587,573; 5,835,409; 5,977,585. Foreign patents and additional patents pending. LIFE RELATED POLICY In situations where semiconductor component failure may endanger life, system designers using this product should design the system with appropriate error detection and correction, redundancy and back-up features to prevent such an occurrence. Xicor's products are not authorized for use in critical components in life support devices or systems. 1. Life support devices or systems are devices or systems which, (a) are intended for surgical implant into the body, or (b) support or sustain life, and whose failure to perform, when properly used in accordance with instructions for use provided in the labeling, can be reasonably expected to result in a significant injury to the user. 2. A critical component is any component of a life support device or system whose failure to perform can be reasonably expected to cause the failure of the life support device or system, or to affect its safety or effectiveness.
REV 4.2 7/8/04
www.xicor.com
Characteristics subject to change without notice.
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